1. Field of the Invention
The present invention relates to a method of fabricating the same, and more particularly to a method of forming a transistor having a strained channel formed by epitaxially growing a semiconductor layer in source and drain regions.
2. Description of the Related Art
As a semiconductor device has been highly integrated, a gate length of a transistor is reduced and thus a channel length of the transistor also becomes smaller. As the channel length is reduced, effect of a source and a drain on electric field or electric potential in a channel region becomes significant. This phenomenon refers to as a short channel effect. Carrier mobility is reduced by the short channel effect and the performance of the transistor is deteriorated by contact parasitic resistance. Therefore, there have been various studies on methods capable of improving the performance of the transistor while reducing the gate length.
Among the methods, there is a method using a local strained effect which increases the movement of electrons or holes by generating tension or compression force in a channel region under a gate of a transistor. A representative method using the local strained effect is a method of forming tension in a channel region by changing a kind and a thickness of a layer that acts as an etch stop layer during a process of forming a contact hole in a case of an NMOS transistor, or a method of forming strain in a channel region by filling a recess region through selective epitaxial growth (SEG) with silicon germanium (SiGe) that has a large lattice constant compared to silicon having a lattice constant of 5.43 Å after recessing a source and a drain regions in a case of a PMOS transistor.
In the PMOS transistor, in order to further enhance the carrier mobility by generating larger strain, the composition of Ge in SiGe is increased to a level of, e.g., more than 20%, so that a defect such as a stacking fault may be generated in the recess region. That is, if SiGe is grown with high Ge concentration of more than 20%, as the concentration of Ge increases, a growth mode thereof tends to show an island-type growth mode (Volumer-Weber mode) or heteroepitaxial mode of layer-type and island type growth mode (Stranski-Krastanove mode) rather than a layer type growth mode (Frank-van der Merwe mode) in which the layer is epitaxially grown layer by layer. Therefore, defects such as a stacking fault are generated in an interface of the recess region and the SiGe region.
Furthermore, ion implantation and silicide processes are performed to reduce the contact resistance of the SiGe layer having high Ge concentration. However, sheet resistance is increased on the contrary. That is, at a temperature of 300 K, the electron mobility and hole mobility of Si are 1500 cm2/V-s and 400 cm2/V-s, respectively and those of Ge are 3900 cm2/V-s and 1900 cm2/V-s, respectively. Theoretically, the sheet resistance decreases as the concentration of Ge in SiGe increases. However, in practice, as the concentration of Ge increases, the sheet resistance increases since a silicide material such as Ni used as a silicide in a Ni silicide process is readily agglomerated on a surface of SiGe.
By the defect such as the stacking fault of SiGe of the source and drain regions, effect of forming a strained channel is reduced. When the sheet resistance of the silicide increases, a leakage current increases and thus increase of the carrier mobility expected by using SiGe can't be achieved. In addition, the above drawbacks deteriorate the performance of the transistor.